Method and circuit for balancing an error signal

ABSTRACT

A circuit for balancing an error signal delivered by an apparatus. When the apparatus is switched on initially, the error signal may be large and thereafter change only slowly with time. The error signal may be a signal which is delivered by a measuring sensor and which is independent of the quantity to be measured. The circuit includes a negative feedback loop 7, 11 which, immediately upon activating or starting the apparatus, feeds back a balancing signal which rapidly compensates the error signal. The circuit also includes components 12-16 for changing the feedback loop when the error signal has been substantially compensated, so that only slow changes in the error signal with a frequency below a selected upper limit frequency are fed back.

BACKGROUND OF THE INVENTION

The present invention relates to a method of balancing anapparatus-produced error signal, which may be large when the apparatusis initially switched on, or activated, but which thereafter changesonly slowly with time, particularly an error signal delivered by ameasuring sensor or like measuring detector which is independent of thequantity being measured. The invention also relates to a circuit for usewhen carrying out the method.

The need to be able to balance an error signal which may be initiallylarge but which, in a steady state condition, changes only very slowlywith time, is found in many different contexts, one example beingmeasuring sensors and the like which are intended to measure differentquantities, these devices normally being incorporated in a measuringbridge.

It is often difficult or impractical to calibrate the measuring bridgeprior to a measuring operation, and the bridge is therewith liable toproduce an error signal, a so-called offset, even before it isinfluenced by a quantity to be measured.

In such a case, one approach is to consider all dynamic signals asuseful signals. Then, by ac coupling the measuring bridge and utilizinga bottom limit frequency which is sufficiently low for the applicationconcerned the system can be caused to measure only the desired, dynamicchanges. Thus, the use of a low limit frequency makes it possible tomeasure also very slow changes. An ac coupled system is normallyobtained by connecting capacitors between the measuring bridge andassociated amplifiers.

In this case, the lower limit frequency of the measuring system is setwith the aid of the time constant determined by the capacitors andresistors included in the system. One drawback with this solution,however, is that the size of the capacitors required increases withdecreasing values of the lower limit frequencies. For example, if alower limit frequency of 1 Hz is desired and reasonable resistancevalues are used in the amplifiers, the capacitors will be in the orderof magnitude of μF. The problem will naturally increase when requiring alower limit frequency of 0.01 Hz, for instance. However, it has beenpossible to solve this problem with the aid of low leakage capacitorsand amplifiers with high impedances.

If the intention is to integrate such equipment on a silicon chip,however, completely new problems arise. Admittedly, capacitors andresistors can be mounted on a silicon chip in addition to transistorsand diodes. However, the larger the capacitors to be produced, the moreuseful chip surface is taken-up, and it is also difficult technically toproduce capacitors above a certain rating, normally a rating of 10-100pF. Thus, when practicing present-day techniques, it is extremelydifficult to integrate ac coupled amplifiers of low bottom-limitfrequencies on a silicon chip.

One alternative to the use of an ac coupled system is to supplyconstantly a balancing or equalizing signal which will compensate theerror signal produced by the measuring sensor. In this regard, if thebridge output signal is returned undamped through a negative feedbackloop, the output signal will be constantly zero. However, the usefulcomponent of the measurement signal, when it appears, will also bebalanced.

SUMMARY OF THE INVENTION

The present invention is based on the realization that this problem canbe solved by making the feedback loop frequency-dependent, when theerror signal to be compensated may be large immediately upon switchingon or activating the apparatus, and thereafter changes only very slowly,for example as a result of system component changes which vary withtemperature or time. The useful measuring signal which reflectsvariations in the quantity to be measured is assumed to vary morequickly than the aforesaid very slow component changes. Thus, also slowchanges in the quantity can be measured, by choosing for the usefulsignals a low bottom limit frequency which is nevertheless higher thanthe slow component changes.

Accordingly, the main object of the present invention is to provide atechnique which makes frequency-dependent feedback of the error signalfrom an apparatus possible, so that an initially large error is balancedvery quickly, and whereafter continuous compensation can be obtainedsolely for slow changes in the error signal.

In accordance with the present invention, the method is particularlycharacterized in that a balancing signal which will rapidly compensatethe initial error signal is delivered to the apparatus via a negativefeedback loop immediately after each time the apparatus is switched on;and in that when the error signal has been substantially balanced, thefeedback loop is changed so that, for as long as the apparatus isswitched on or activated, only slow changes in the error signal willthereafter be fed back, with a frequency which is below an upper limitfrequency that is selected in dependence on the application concerned,whereas other, useful measuring signals are delivered uninfluenced.

In accordance with one preferred embodiment of the invention, thefeedback signal is delivered from a digital-to-analog converter whichobtains its input signal from an up-down counter whose countingdirection is determined by the polarity of the error signal. Theaforesaid frequency-dependent feedback can be achieved by controllingthe counter by means of a high clock frequency when initially balancingthe error signal and thereafter with a lower clock frequency. Thus, thehigh clock frequency initially used will produce a rapidly increasingfeedback signal which quickly balances the error signal, whereas thelower clock frequency used thereafter does not allow rapid changes to betaken into account in the feedback signal.

This feedback function can be achieved without the use of largecapacitors and is thus well suited for silicon chip integration.

In accordance with one embodiment, the error signal is compared with areference signal and the clock frequency is changed when the comparisonshows that the error signal has been balanced. The lower clock frequencyis then maintained during the time that the measuring bridge isconnected or operative.

As an alternative to this comparison, the clock frequency can be changedfrom the higher to the lower frequency level after a predeterminedlength of time has lapsed after switching-on the apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described in more detail with reference to anexemplifying embodiment thereof illustrated in the form of schematicblock diagrams shown in the accompanying drawings.

FIG. 1 illustrates a measuring bridge provided with a feedback loop inaccordance with the invention, for balancing the error signal.

FIG. 2 illustrates the feedback loop of FIG. 1 in more detail.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The apparatus illustrated in FIG. 1 includes a conventional measuringbridge 1 which is connected between the voltages +V and -V. The bridgeoutput signal is delivered to an amplifier 2, the output signal ofwhich, in turn, is delivered to a comparator 3 which receives areference signal on another input 4 thereof. The comparator 3 has anoutput 5 which delivers a positive signal to an input 6 of a counter 7when the output signal of the amplifier 2 is positive and larger thanthe reference signal on the input 4 of the comparator 3.

The apparatus also includes a clock frequency source 8 which isconnected to an input 9 of the counter 7. When the aforesaid signal onthe counter input 6 is positive, the counter 7 will count upwardssynchronized with the clock frequency from the source 8. When the outputsignal of the amplifier 2 is negative, however, the comparator 3 willdeliver a signal to the input 6 of the counter 7, which sets the counterso as to count down synchronized with said clock frequency.

The counter 7 has a number of binary outputs 10 which are connected tocorresponding inputs of a digital-to-analog converter 11. The analogoutput signal of the converter 11 is returned to the negative input ofthe input amplifier 2.

The circuit illustrated in FIG. 1 operates in the following manner:

When the output signal of the amplifier 2 is positive and greater thanthe reference signal on the input 4 of the comparator 3, it delivers apositive output signal to the counter 7. As before mentioned, thiscauses the counter to count upwards to successively higher valuessynchronized with the clock frequency from the source 8, these valuesbeing converted in the digital-to-analog converter 11 to an analogsignal which increases the input signal on the negative terminal of theamplifier 2. The amplifier 2 will, in this way, pass towards a balancedstate. When the amplifier is set, so that its output signal becomesnegative, the comparator 3 is reset to zero and the input 6 of thecounter 7 is also reset to zero, whereupon the counter counts downwardsand the analog feedback signal from the digital-to-analog converter 11decreases. The amplifier 2 will then again produce a positive outputsignal, and so on. The counter 7 will thus count alternately upwards anddownwards, so as to maintain the amplifier at its balance point.

By choosing a source 8 of a high clock frequency, the error signalapplied to the amplifier 2 can be balanced very rapidly when theapparatus is initially switched on, at which time the error signal ofthe measuring bridge 1 can be very large.

However, subsequent to initially balancing the measuring bridge 1, noneof the incoming, useful measuring signals should be compensated inconjunction with the measuring of desired quantities, these signalsbeing delivered at the output 17. On the other hand, it is desirable tocompensate for such slow changes in the error signal as those that areliable to occur as a result of component temperature changes, componentaging or similar component phenomena in the measuring bridge components.

This problem can be solved by using, for steady state operation, a clocksignal of lower frequency for the counter 7, meaning that measuringsignals from the amplifier 2 in response to changes of the quantity tobe measured at a higher frequency cannot be compensated because thespeed of the counter is too low. The higher frequencies thus pass to theoutput 17 essentially uninfluenced by the negative feedback. In thisregard, the upper limit frequency for which the circuit is able tocompensate by said feedback is completely dependent on the clockfrequency from the source 8. The higher the clock frequency, the morequickly the bridge is balanced and the higher the upper limit frequencybecomes for signals which are compensated. Thus, by choosing a low clockfrequency, it is possible to compensate only for very slowly varyingerror signals. A clock frequency of such low value cannot be used,how-ever, when initially balancing the bridge, since the time requiredherefor would be much too long for the majority of applications.

FIG. 2 illustrates a further development of the feedback loop shown inFIG. 1, which is so constructed as to enable the clock frequency to beswitched between a high frequency in conjunction with initial balancingof the bridge and a much lower frequency for use during staedy stateoperation. The same reference numerals as those used in FIG. 1 have beenused in FIG. 2 to identify corresponding components. At the time ofstarting the apparatus, it is assumed that the counter 7 is at 0 andthat flip-flop 12 is in a zero-state and that the clock signal source 8has a frequency of, e.g, 1000 Hz. This frequency is divided in afrequency divider 13 down to a frequency of 1 Hz, for example.

When the apparatus is started, the bridge is assumed to be unbalanced,causing the comparator 3 to deliver a positive output signal, and thecounter 7 begins to count upwards. The clock signal of frequency 1000 Hztherewith passes through an AND-gate 14 which has an inverting inputconnected to the flip-flop 12, and passes to the clock input of thecounter 7 through an OR-gate 15. The counter will thus quickly countupwards and balance the error signal of the measuring bridge 1 by meansof the output signal from the digital-to-analog converter 11 (see FIG.1). The comparator 3 switches over and is set to zero immediately theamplifier 2 switches to a negative output signal, therewith changing thedirection in which the counter 7 counts. When the comparator 3 is set tozero, the flip-flop 12 is also switched, therewith blocking the AND-gate14 and opening an AND-gate 16. A clock frequency divided by 1000 willnow be applied to the counter 7, through the AND-gate 16 and the OR-gate15. The counter therewith counts down at a rate of one step/second ascompared with the earlier upward count of 1000 steps/second. Theflip-flop 12 remains in this state for as long as the apparatus isswitched-on.

Thus, the aforedescribed coupling enables the measuring bridge 1 to bebalanced very quickly when the apparatus is switched on, with the aid ofa negative feedback of high frequency, and is then maintained in balanceby compensating for slow changes or drift which may be due to changes inthe apparatus components, as a result of the negative feedback of onlylow-frequency signals with a predetermined maximum highest frequency.The measuring bridge can thus also be used to measure slow signals,provided that the signals are faster than the aforesaid highestfrequency, which can be given a very low value, however. This can beachieved without the use of large capacitors.

Thus, in practice, the invention enables a measuring system to beconstructed with a bottom limit frequency of 0.01 Hz while usingcapacitors which do not exceed 0 pF. In this regard all of theaforedescribed functions can be integrated on a silicon chip without theuse of any external components, which provides wide possibilities ofintegrating measuring sensors and adaptation-electronics in a highlyminiaturized form.

Although the invention has been described in the aforegoing withreference to a preferred embodiment thereof, it will be understood thatthis embodiment can be modified and varied in several respects withinthe scope of the following claims. For example, instead of basing theclock signal change on a comparison of the error signal with a referencesignal, this change may also be effected after a predetermined time haslapsed after switching on the apparatus. Furthermore, more than twolevels of clock frequency may be used and activated, for instance independence on the size of the error signal. Instead of starting from 0,the counter may start from a minimum value which corresponds to the mostprobable imbalance value. This enables the time taken to achieve theinitial balancing process to be further shortened. The aforesaidfrequency values have been given only by way of example.

According to the aforegoing, an apparatus can be used in many contexts,such as in systems for so-called active suspension of automobiles andtrains, temperature control equipment, self-calibrating weighingmachines, etc.

When the requirement for small capacitors is not equally pronounced, afunction corresponding to the aforedescribed function can be achieved byusing a frequency-dependent negative feedback loop which includes anRC-circuit where the resistance can be short-circuited at the time ofinitially balancing the bridge. When the resistance is subsequentlyconnected, there is obtained a time constant which is determined by thecomponent values and which determines the limit frequency of thesefrequencies at which compensation is achieved.

I claim:
 1. A method of balancing a large initial, intrinsic errorsignal in a measuring apparatus only when initially switching theapparatus on, said error signal thereafter changing only slowly withtime, and being independent of a quantity to be measured, comprising thesteps of:a) delivering a balancing signal to the apparatus through anegative feedback loop immediately after the apparatus is switched on,said balancing signal functioning to rapidly compensate the initialerror signal; and b) changing the feedback loop after the initial errorsignal has been substantially balanced so that thereafter only slowchanges in the error signal that have a frequency below a selected upperlimit are fed back, while higher frequency measurement signals areoutput substantially unbalanced for as long as the apparatus remainsswitched on.
 2. A method according to claim 1, wherein the feedbacksignal is delivered from a digital-to-analog converter having an inputsignal obtained from an up-down counter; and the count direction of thecounter is determined by the polarity of the error signal.
 3. A methodaccording to claim 2, wherein the counter is controlled by means of ahigh clock frequency when initially balancing the error signal, and at alower clock frequency thereafter.
 4. A method according to claim 3,wherein the error signal is compared with a reference signal, and theclock frequency is changed when the comparison shows that the errorsignal has been balanced.
 5. A method according to claim 4, wherein thelower clock frequency is maintained for as long as the apparatus remainsswitched on.
 6. A method according to claim 3, wherein the clockfrequency is changed subsequent to the passage of a predetermined lengthof time after the apparatus is switched on.
 7. A circuit for balancing alarge initial, intrinsic error signal in a measuring apparatus only wheninitially switching the apparatus on, said error signal thereafterchanging only slowly with time, and being independent of a quantity tobe measured, comprising:a) negative feedback loop means (7, 11) forimmediately feeding back a balancing signal which rapidly compensatesthe initial error signal in response to the apparatus being switched on,b) means (12, 13, 16) for changing the feedback loop after the initialerror signal has been substantially balanced so that thereafter onlyslow changes in the error signal that have a frequency below a selectedupper limit are fed back for as long as the apparatus remains switchedon, and c) output means (17) for delivering higher frequency measuringsignals in a substantially unbalanced state.
 8. A circuit according toclaim 7, wherein the feedback loop includes a digital-to-analogconverter (11) and an up-down counter (7) connected to an input of theconverter, and the count direction is controlled by the polarity of theerror signal.
 9. A circuit according to claim 8, further comprisingmeans (12-16) for controlling the counter with a high clock frequencyduring the initial balancing of the error signal, and with a lower clockfrequency thereafter.
 10. A circuit according to claim 9, furthercomprising comparison means (3) for comparing the error signal with areference signal (4), and means for changing the clock frequency inresponse to the output signal of the comparison means.